The present invention relates to a storage control system using plural buffer address arrays, and in particular, to a storage control system comprising a first buffer address array as a buffer storage directory for registering thereto an address of data copied from a shared storage into a buffer storage of each processor and a second buffer address array independent of the first buffer address array and which is provided for a store address check requested from another processor.
A data processing system reads data such as instructions and operands from a main storage and supplies this data to a processor to execute data processing. The main storage has a large capacity and requires a longer access time for accessing data therein as compared with the processing speed of the processor. Consequently, a required data item can be obtained for use in a higher speed as follows. A processor is provided with a buffer storage which has a higher access speed and a smaller capacity than the main storage and the processor accesses the buffer storage onto which data stored in the main storage and to be used more frequently is copied. Whether the required data exists in the buffer (in-buffer state) or not (not-in-buffer state) is determined by referring to an associated buffer address array provided as a directory.
In a multiprocessor system including processors having such buffer storages and which share the main storage, if a processor updates a data item stored at a given address in the main storage and if the data item stored at the given address has been retained in a buffer storage of another processor, there appears a conflict between the data items on the buffer and main storages. The U.S. Pat. No. 3,618,040 has disclosed a multiprocessor system in which the main storage is shared among processors having buffer storages. In accordance with the U.S. Pat. No. 3,618,040, a store address for storing a data item is broadcast to the other processors, which then refer to a buffer address array in order to determine whether or not the broadcast address has been registered to the buffer address array. If this is the case, the registered address is made to be invalid (canceled).
In accordance with the U.S. Pat. No. 4,056,844, the buffer address array described above is defined as a first address array and there is provided a second address array for storing the same data as the first address array. The address broadcast from another processor is checked for the registration thereof by referring to the second address array. This provision prevents the referring operation of the processor associated with the first address array from being blocked by the referring operation thereof with respect to the address broadcast from the other processor.
Update operations for the first and second arrays are as follows. When the data at a requested address is not found in the buffer storage and the data of a block (for instance, 64 bytes) at locations including the requested address is replaced by executing a block transfer from the main storage to the buffer storage, the address of the replaced block is registered, and when an address broadcast from another processor is retained, the address registration is canceled (to be invalid).
Conventionally, the first control table (address array) and the second control table (address array) are updated in the manner described below.
(1) For a block transfer, an update request for the first address array is issued when the data transfer from the main storage to the buffer memory (storage) is completed, while an update request for the second address array is made when a read (fetch) request is issued to the main storage. As described above, the update operations of the first and second address arrays are executed independently to each other.
(2) For a write (store) operation by another processor to the main storage, an update request is issued first to the second address array when a fetch request is made to the main storage, and thereafter the first address array is updated.
(3) When a conflict takes place in the update operations in (1) and (2) above, the first address array is updated regardless of the sequence of processing for the main storage, while the second address array is updated in accordance with the sequence for accessing the main storage.
The prior art has the following problems. For example, in a program in which a first processor executes a store request in the order of address X and address Y on a main storage conducting communications with another system and a second processor fetches data stored at address X after confirming that the first processor has updated data at address Y (in this program, it is naturally assumed that data at address X has been updated if the update at address Y has been completed), the first processor executes the store operation first at address X then at address Y, while the second processor carries out the fetch operation in the sequence of address Y and address X. For a Y address fetch request issued from the own processor, a check is made to determine whether or not the pertinent data has been registered to the buffer memory by use of the first address array associated with the second processor. If this is the case, the data is read from the buffer memory; otherwise, a block transfer is executed from the main storage to the buffer storage. If the request from the first processor for a store operation at address Y of the main storage has been finished in this case, the second processor issues a request to read data stored at address X after the block transfer is completed, so the first address array is checked to determine whether or not the relevant data has been registered to the buffer storage. If the operation for invalidating the data of the second address array due to the request from the first processor for storing data at address X in the main storage has been delayed and has not been completed, the X address registered to the first address array in advance remains unchanged, thus the second processor reads the data from the buffer memory. The data fetched contains an old information, that is, the second processor has obtained an invalid data item.
To prevent such a fetch operation which reads an invalid data item, the following techniques have been conventionally employed. A serialize instruction is inserted between a Y address fetch operation and an X address fetch operation in order to check the completion of the invalidating operation for the buffer storage caused by a store request from the first processor for storing data at address X (restriction on the program), or the second processor is prevented from referring to the buffer storage when an invalidating operation is executed on the second address array and the first address array (if it is found by checking the second address array that the data has been registered) due to a store request from the first processor for storing data in the main storage. However, the former method imposes a severe restriction on the programmer and the inserted serialize instruction lowers the performance, whereas the latter method also reduces the performance because the operation executed to refer to the buffer memory is unconditionally prevented.